Nonlinear phase detector

ABSTRACT

PHASE RESPONSIVE CIRCUITRY WHEREIN A NONLINEAR RESPONSE TO PHASE ERROR IS OBTAINED BY PROVIDING FIRST AND SECOND PHASE DETECTORS, EACH FOR COMPARING THE PHASE OF AN INPUT TO A REFERENCE SIGNAL WITH TRIGGERING MEANS RESPONSIVE TO THE OUTPUT OF EACH PHASE DETECTOR. THE FIRST TRIGGERING MEANS PROVIDES A LARGE POSITIVE LEVEL OUTPUT AND A LARGE NEGATIVE OUTPUT WHEN ITS INPUT IS POSITIVE AND NEGATIVE, RESPECTIVELY. A SECOND TRTIGGERING MEANS ENABLES A GATE TO PASS THE OUTPUT FROM SAID FIRST TRIGGERING MEANS TO A SUMMING CIRCUIT WHEREBY THE OUTPUT FROM SAID PHASE RESPONSIVE CIRCUITRY IS NONLINEARLY INCREASED FOR PHASE ERRORS EXCEEDING A PREDETERMINED DIFFERENCE.

United States Patent ln entor George welfi 3.336.534 8/1967 Gluth .4331/12 I N 3,403,355 9/1968 Takada 331/25X 25:3 p 21 1969 PrimaryExaminer-Roy Lake Patented June 1971 Assistant ExaminerSiegfried H.Grimm Assignee Westinghouse Electric Corporation A0mey; F' Henson andKhpfel Pittsburgh, Pa.

NON-LINEAR PHASE DETECTOR 10 Claims 4 Drawing Figs ABSTRACT: Phaseresponsive c rcuitry wherein a nonlinear response to phase error isobtained by providing first and [1.8. CI 331/12, Second phase detectors,each f comparing the phase f an 307/232. 328/1 33, 3 input to areference signal with triggering means responsive to Int. Cl H03b 3/04,the output f each phase daemon The fi t triggering means 13/00 providesa large positive level output and a large negative out- Field of Search331/11, 12, put when i input i positive and negative, respectively. A25; 328/133 134; 307/232 second triggering means enables a ate to passthe output from Reterences Cited said first triggering means to asumming circuit whereby the output from said phase responsive circuitryis nonlinearly in- UNITED STATES PATENTS creased for phase errorsexceeding a predetermined dif- 1,448 8/1963 Costas 33l/12X ference.

VCO R EF ERE NCE l N PUT 2o 2 5 PHASE SIGNAL INPUT DETEICTOR 24 (28 1 lSCHMITT 90 PHASE l 30 SHIFT NONLINEAR PHASE DETECTOR OUTPUT PHASESCHMITT 26 DETEgTOR 7 TR ICZSGER Patented June 28, 1971 3,588,734

7 4 I07 8? 2 VOLTAGE l 2, PHASE FILTER CONTROLLED 7 DETEtfii OSCILLATORFlG O A Z'IT 3" Tr 1T 3 ERROR PRIOR ART FIG. 2.

(b OUTPUT(UN|TS) NONLINEAR PHASE DETECTOR OUTPUT PHASE DETECTORPHASEDETECTOR ZOOUTPUT 22 OUTPUT -|ao -9o; x q) ERROR +9o +|ao V F|G.4.

vco REFERENCE INPU ,20 2 PHASE SIGNALINPUT -DETEICTOR 1 F IG.3. 90PHASESHIFT NONLINEAR 22 PHASE DETECTOR 7 3 OUTPUT PHASE DETEgTOR wumesses:INVENTOR George R. WeHi BY .T 5M ft ATTORNEY NON-LINEAR PHASl-lIII'I'I'FKT'IOR BACKGROUND OF THE INVENTION 1. Field ofthe Invention Thepresent invention relates generally to phase responsive circuitry andmore particularly relates to nonlinear phase detectors for phase-lockedloops and the like.

2. Description oi'the Prior Art Conventional phase detectors haveresponse characteristics which are insufficient when the initial phaseerror or difference is near an odd multiple of 1r radians.

Such limited response results in phase-locked loops requiring manycarrier cycles to synchronize. So-called linear phase detectors providebetter response characteristics thereby allowing relatively fastsynchronization in a locked loop circuit, as fast as cycles for theworst initial condition. Unfortunately the implementation of linearphase detectors is relatively complex. The inherent delays introduced bylinear phase detection circuits can cause loop instabilities which canonly be remedied by reduction in loop gain and consequent increase insynchronization time of a phase-locked loop.

SUMMARY OF THE INVENTION An object of the present invention is toprovide phase responsive circuitry having a nonlinear output.

Another object of the present invention is to provide phase responsivecircuitry which when used in a phase-locked loop provides fastersynchronization time, simpler implementation and more stable loopoperation than heretofore available.

Briefly, the present invention accomplishes the above-cited objects aswell as other objects and advantages by providing for circuitry forcomparing an input and a reference signal of different phase andproducing an output signal which is proportional to the phase differencefor small phase differences but providing an output signal which is alarger nonlinear function of the phase difference for large phasedifferences between the two signals being compared. The output alsoindicates the polarity of the phase difference. In phase lockedoscillator control loops short synchronization time is thereby achieved.

BRIEF DESCRIPTION OF THE DRAWINGS Further objects and advantages of thepresent invention will be more readily apparent from the followingdetail description taken in conjunction with the drawings in which:

FIG. I is a schematic block diagram of one use of the present invention;

FIG. 2 is a graphical representation of conventional responsesobtainable with circuitry ofthe prior art;

FIG. 3 is a schematic block diagram of an illustrative embodiment of thepresent invention; and

FIG. 4 is a graphic illustration of the response characteristicsobtainable when practicing the invention.

FIG. 1 shows the configuration of the essential elements ofaphase-locked loop. In general, the input carrier signal 2 may or may notbe amplitude or frequency modulated. The phase detector is a timevarying nonlinear element whose average output is a periodic function ofthe phase difference between the input carrier 2 and a reference signal6 fed back from a voltage controlled oscillator 8. A filter 10 connectsthe nonlinear response output from the phase detector 4 to the voltagecontrolled oscillator 8 to change its frequency in such a way as to pullit into exact correspondence with the signal input 2. The voltagecontrolled oscillator 8 provides an output l2 represented by cos[m(f)r+] where wU) is proportional to the input M to the oscillator 8 attime, t. The output 12 is returned to the phase detector ll as areference input signal 6 to complete the feedback loop.

Conventional phase detectors have response characteristics such ascurves A and B in FIG. 2. Phase-locked loops with conventional phasedetectors require many carrier cycles to synchronize when the initialphase error is near an odd multiple 4 1r radians. In many instances. thesynchronization time will typically exceed 20 cycles. So-called linearphase detectors with response characteristics such as curve C in FIG. 2can give relatively fast synchronization-as fast as 10 cycles for theworst initial condition. However, the implementation of linear phasedetectors is relatively complex. The inherent delays introduced bylinear phase detection circuits can cause loop instabilities which canalso be remedied by reduction in loop gain and consequent increase insynchronization time.

A nonlinear phase detector capable of providing faster synchronizationtime and more stable loop operation is shown in the illustrativeembodiment of FIG. 3. The input signal 2 is connected to phase detectors20 and 22. The other input to the phase detector 20 is a referencesignal, which can be from a voltage controlled oscillator. The otherinput to the phase detector 22 is also the reference input but shiftedin phase by a phase shift circuit 24.

The output of the first phase detector 20 is as shown by the staggeredcurve in FIG. 4. This output is fed to a summing circuit 26 and also toa trigger 28. Schmitt trigger 28 has a bipolar output and will produce alarge positive level output when its input is positive, and a largenegative output when its input is negative. The output from the Schmitttrigger 23 however will not be allowed through to the summing circuit 26by a gate 30 until the gate 30 is enabled. Such an enabling circuit isprovided by a Schmitt trigger 32. The Schmitt trigger 32 is adjusted totrigger when the phase error exceeds 45. Schmitt trigger 32 will onlyprovide an enabling signal when the phase error exceeds a predeterminedvalue when compared with the nonshifted reference signal.

Upon being enabled, the gate 30 allows the output from the Schmitttrigger 28 to be summed with the output of the phase detector 20. Thus,a nonlinear phase detector response characteristic is obtained as shownby the solid lined curve of FIG. 4.

From FIG. 4, it can be seen that the Schmitt trigger 28 in creases theoutput of the phase detector for errors over 45 by adding a constantvoltage to the output of the phase detector 20.

When the phase detector 22 has an output exceeding one unit then theSchmitt trigger 32 assumes an output state herein designated as a zero.When the phase detector 22 has an output less than one unit then thetrigger 32 has an output herein designated as a binary one, therebyenabling the gate 30.

The Schmitt trigger 28 provides a large positive or large negativesignal which is responsive to the polarity of the phase shift of theinput compared to the reference signal. The output of the Schmitttrigger 28 however is not connected to the summing circuit 26 until anenabling signal is present at the gate 30. The result is, from FIG. 4,that a nonlinear output will occur when the phase error exceeds apredetermined value herein designated as 45.

While the present invention has been described with a degree ofparticularity for the purpose of illustration, it is to be understoodthat all modifications, alterations and substitutions within the spiritand scope of the present invention are herein meant to be inclined. Forexample, when the nonlinear phase detector is used in a phase-lockedloop such as shown in FIG. 1, the output from the summing circuit 26 isconnected to the filter I0 and the reference input is derived from thevoltage controlled oscillator 8. Of course, other uses of the nonlinearphase detector in accordance with the present invention may also bemade.

I claim:

1. Phase responsive circuitry comprising, in combination; first andsecond phase detectors; means for applying an input, the phase of whichis to be detected. to said first and second phase detectors; means forapplying a reference input to said first phase detector; means forapplying a phase shifted reference input to said second phase detector;first triggering means for providing an output signal of one polaritywhen the phase is leading the reference input and an output signal ofother polarity when the phase is lagging the reference input;

means for summing the output from said first phase detector with theoutput from said first triggering means; gating means for connecting theoutput from said first triggering means to said summing means; andsecond triggering means for providing an enabling signal to said gatingmeans when said input exceeds the reference input by a predeterminedphase difference.

2. The circuitry of claim 1 wherein said first and second phasedetectors each provide an output responsive to the phase differencebetween said input and the reference input.

3. The circuitry of claim I wherein the phase shifted reference inputapplied to said second phase detector is 90 displaced in phase from thereference input to said first phase detector.

4. The circuitry ofelaim I wherein the predetermined phase difference.which when exceeded causes said second triggering means to provide saidenabling signal, is 45.

5. The circuitry of claim I wherein said first triggering means is aSchmitt trigger having a bipolar output and which will produce a largepositive level output when its input is posi tive, and a large negativeoutput when its input is negative.

6. The circuitry of claim I wherein said second triggering means is aSchmitt trigger providing an enabling signal to said gating means whenthe output of said second phase shifting means is less than apredetermined magnitude.

7. The combination of claim 1, further including; filter means forfiltering noise from the output of said means for summing; voltagecontrolled oscillator means responsive to the filtered output forproviding a signal which follows the phase of said input being detected;and means for feeding hack the output from said voltage controlledoscillator means as said reference signal.

8. The combination ofelaim 7, wherein said filter means is a low passfilter with narrow pass bandwidth.

9 The circuitry of claim 7 wherein said filter means is linear and timeinvariant.

l0. 'lhe circuitry ofelaim 9 wherein said voltage controlled oscillatormeans produces an output cos [w(f)r+] where (00) is proportional to saidfiltered output at time I.

